This invention relates to low-dropout voltage regulators and to circuits for improving the response of a low-dropout voltage regulator to variations in the load of the regulator.
Some circuits need to be operated with a constant voltage to provide a reference voltage or a stable operation supply voltage. The low-dropout voltage regulator, typically called LDO, is usually designed for this case when the load current varies. The LDO regulator is a linear regulator with a low dropout, i.e., the minimum voltage required across the regulator to maintain a regulated output voltage. Like the standard regulator, the LDO regulator has a pass element which is connected between the input and output terminals of the regulator. The input voltage to the regulator minus the voltage drop across the pass element is the output voltage. In the case of the LDO regulator, the voltage drop is small (i.e., low), less than a few hundred mV, say 300 mV, and may be less than 100 mV. The conventional LDO regulator has basically a PMOS FET (P-type Metal-Oxide-Semiconductor Field-Effect Transistor) for a pass element and a feedback amplifier connected to control the PMOS FET. The amplifier has one of its input terminals connected to the LDO output and a second input terminal connected to some reference voltage. The output terminal of the amplifier is connected directly or indirectly, to the gate of the PMOS FET.
The LDO regulator is used in many applications and can be part of an integrated circuit or as an integrated circuit itself. But the LDO regulator has limitations. For example, the response of the LDO regulator may not be as fast as required for certain applications. The regulator may not be able to handle sudden variations in the load current with resulting variations in the voltage at the LDO regulator output.
Therefore what is needed is an efficient and economical way of addressing variations in the load current and keeping the output voltage of the LDO regulator constant.